Anchor Customer Presentations in SPIE Advanced Lithography Conference 2010, San Jose Convention Center

With broadened applications of Anchor's products and increased collaborations with our customers, we are glad to see our tools have been used more and more in both IC design and manufacturing, including the area of yield enhancement. As a result, we are able to highlight some of the customer applications in this year's SPIE Advanced Lithography Conference in San Jose; in particular, how to apply Anchor's pattern-centric technologies to improve yield in advanced FPGA devices. We encourage you to attend the following sessions to find out by yourself. Thank you!

7641-10, Thursday, Feb. 25, Session 3 8:00AM:

Systematic failure debug and defective pattern extraction for FPGA product-yield improvement
Author(s): Cinti X. Chen, Joe W. Zhao, Xilinx, Inc. (United States); Ping Zhang, Raymond Y. Xu, Anchor Semiconductor, Inc. (United States).
Abstract: In this paper, we have developed a new method for systematic failure detections. This integrated approach can establish correlation and connectivity of design layout, physical verification, wafer defect inspection, product testing patterns and wafer sort bit maps. By overlaying KLA defect locations and design gds locations, by extracting similar defective patterns and correlating them to defect class, test pattern failure and sort bitmaps, we can identify defective layout patterns, process marginal weak-spots and repetitive patterns and cluster defects sensitive to KLA inspections. The extracted defective patterns of the failing cells can help designers, OPC engineers and Fab engineers to quickly pinpoint systematic failures thus improve product performance and yield ramp up.

7641-36, Wednesday, Feb. 24 Poster session, 6:00-8:00PM:

Detection of OPC conflict edges through MEEF/NILS analysis
Author(s): Lifu Chang, Chang-Il Choi, Semiconductor Manufacturing International Corp. (China); Guojie Cheng, Abhishek Vikram, Gary Zhang, Anchor Semiconductor, Inc. (China); Bo Su, Anchor Semiconductor, Inc. (United States)
Abstract: In this paper, we present an adaptive DFM (Design for Manufacturability) flow based on MEEF/NILS analysis. We demonstrate the existence of OPC conflict edge hotspots using MEEF/NILS analysis, in particular, the MEEF increase after OPC on those edges actually has smaller process window than pre-OPC ones. Based on the finding, we propose a practical methodology of detecting design related OPC edge conflicting hotspots in a pattern centric software-based DFM flow. The methodology is aiming at detecting patterns containing such conflicting edges and pursuing layout actions on the design side to eliminate this issue. We validate the flow using a real design case. In addition, the OPC edge conflicting hotspots can be clipped and saved in a designated pattern library as hotspot templates, and incoming designs can be quickly screened using exact and similar pattern search with those saved templates in the library.