Easy-to-Adopt Solution for Huge OPC Cost Savings and Performance Acceleration

Anchor Semiconductor is demonstrating our new product NanoScope™ POA (Pattern-based OPC Accelerator) at SPIE Advanced Lithography 2009. This software product accelerates OPC generation by using OPC pattern library and OPC pattern installation. It has undergone rigorous testing at leading-edge customer sites for multiple designs of advanced technology nodes.

Benefits of NanoScope™ POA (Pattern-based OPC Accelerator):

• NanoScope™ POA provides users at least 10 times CPU time reduction for both logic and memory circuits over conventional model based OPC flow. Bigger gains are expected for designs with highly repeated cells and patterns.
• NanoScope™ POA produces more consistent OPC results compared with conventional flow. It guarantees same pattern has same OPC. Quality is better controlled with OPC pattern library.
• The solution is very easy to adopt without changes to simulation models and OPC recipes.
• By adopting NanoScope™ POA, any heavy user of OPC generation tools can easily cut the traditional OPC tool usage by 50% or more and at the same time achieve multiple times of performance improvement.

We are also demonstrating our products NanoScope™ HPA (Hotspot Pattern Analyzer) and NanoScope™ DPL (Defect Pattern Library). Following the introduction at SPIE 2008, we have received strong acceptance from leading foundries, IDMs and mask houses. These products now have many enriched functions targeting mission critical applications.

Highlighted applications and benefits of NanoScope™ HPA (Hotspot Pattern Analyzer):

• Effective handling of large number hotspots from high sensitivity metrology and inspection with pattern and pattern similarity based grouping. It reduces 1 million plus hotspots to thousands or less pattern groups without overlooking significant information.
• Pattern based analysis for hotspots reported by litho simulation tools of post-OPC verification and layout process sensitivity checking (LPC). Defect pattern library and fast pattern search enable pre-emptive strategies for higher yield in both design and manufacturing stages.
• Pattern analysis and grouping for wafer defects. Criticality filtering by pattern repeating, defect size and location, design intent, DFM rules, litho simulation, and more. Guide effective inspection recipe calibration and defect review sampling.