The NanoScope™ DFM platform applies Anchor's patent-pending pattern-centric technologies and integrates comprehensive layout analysis with advanced technologies. It is uniquely capable of providing solutions to meet the patterning challenges. The NanoScope platform enables a family of products covers a wide range of applications, include semiconductor design hot-spot identification, special RET and OPC, OPC verification, photo mask inspection, silicon wafer printing and defect inspection. Advanced lithography modeling enables pattern-centric imaging characterization down to 32 nm technology node. Using Anchor's tools, our customers have successfully shortened time-to-yield and time-to-profitability.

NanoScope DFM platform and product family have the following major solutions and engines to address the needs in design layout pattern transfer to silicon manufacturing.

• NanoScope-HPA™ provides solutions for analysis of different types of violations found from design to manufacturing. It takes hot-spot reports from tools of OPC verification or layout process sensitivity checking. Pattern and cell extraction quickly identify repeating patterns among violations. Through regrouping, sorting, filtering, and re-classification, it enables effective hot-spot disposition and status tracking.
• NanoScope-DPE™ (Design Pattern Explorer) is a unique whole chip design layout analysis and pattern search tool. With proprietary pattern search techniques, NanoScope-DPE is capable to find potential hard-to-process patterns easily for any given IC designs. The DPE reports can directly correlate with many yield-related defect/hotspot inspection and metrology reports in determining yield sensitive patterns, pattern signatures and database regions.
• NanoScope-DPL™ (Defect Pattern Library) DPL provides knowledge sharing and reuse, allows users to save patterns from different sources: litho-unfriendly patterns from OPC verification, problematic patterns in mask making, or yield limiting patterns in wafer printing. Using DPL as a pool of pattern samples, the built-in fast pattern search can easily identify (marker) those patterns in early design phase.
• NanoScope-POA™ (Pattern based OPC Accelerator) is a significant cost and time saving software solution for model-based Optical Proximity Correction (OPC) at advanced technology nodes. With its powerful, proprietary pattern-centric approach, the tool analyzes full chip design space geometry information to create unique pattern library and reuses OPC data for matched patterns in the library to improve performance efficiency. POA has gone through rigorous testing at some leading edge customer sites for full chip designs, and the technology has proven itself to be a time-to-mask saver.
• NanoScope-PRV™ is a model-based full chip Post-RET/OPC verification software solution. Its production-proven technology leads the industry in accurate patterning process modeling, comprehensive defect inspection, and process window limiter pattern extractions. It provides inspection accuracy with no compromise in performance.
• Lithography Modelling is an advanced process modeling engine that simulates physical lithography and photoresist processes in transferring the design layout to wafer imaging patterns. The latest enhancement includes immersion lithography process with state-of-the-art accuracy for 32nm node and below.