|
NanoScope™ DFM Platform
The NanoScope™ DFM platform applies Anchor’s patent-pending pattern-centric technologies and integrates comprehensive layout analysis with advanced technologies. It is uniquely capable of providing solutions to meet the patterning challenges. The NanoScope platform enables a family of products covering a wide range of applications, include design hotspot identification, special RET and OPC, OPC verification, photomask manufacturing and silicon wafer printing. Advanced lithography modeling enables imaging characterization down to 45 nm technology node. Using Anchor’s tools, our customers have successfully shortened yield learning curve and time-to-profitability.
The NanoScope DFM platform and product family have the following major solutions and engines to address the needs in design pattern transfer to silicon.
Product Solutions and Engines:
- NanoScope-PRV™ is a model-based full chip post-RET/OPC verification software solution. Its production-proven technology leads the industry in accurate patterning process modeling, comprehensive OPC defect inspection, and process window limiter pattern extractions. It provides inspection accuracy with no compromise in performance.
- Hotspot Pattern Analyzer provides analysis functions of different types of violations found from design to manufacturing. It takes hotspot reports from tools such as OPC verification or layout process sensitivity checking. Pattern and cell extractions quickly identify repeating patterns among violations. Through regrouping, sorting, filtering, and re-classification, it enables effective hotspot disposition and status tracking.
- NanoScope-DPL™ (Defect Pattern Library) provides patterning knowledge sharing and reuse. DPL allows users to save pattern clips from different sources: litho-unfriendly patterns from design or OPC verification, problematic patterns in mask making, or yield limiting patterns in wafer printing. Using DPL as a pool of pattern samples, the built-in fast pattern search function can easily identify and marker those patterns even in the early design phases.
- NanoScope-DFP™ (Design for Patterning) is a manufacturability-aware lithographic DRC for IC design prior to tapeout. It complements traditional rule-based DRC to ensure lithographic-friendly layout. DFP has successfully completed TSMC’s qualification for accuracy, performance, and usability. It supports and integrates with customer’s existing design and verification methodologies.
- Lithography Modelling is an advanced process modeling engine that simulates physical lithography and photoresist processes in transferring design layout to wafer imaging patterns. The latest enhancement includes immersion lithography process with state-of-the-art accuracy for 45nm node.
|
