NanoScope-DFP™ (Design for Patterning) is a manufacturability-aware lithographic DRC for IC design prior to tapeout. It complements traditional rule-based DRC to ensure lithographic-friendly layout. DFP has successfully completed TSMC’s qualification for accuracy, performance, and usability at 65nm node. It supports and integrates with customer’s existing design and verification methodology.

Features and Benefits:

• Lithographic pattern-based library with DFM Score Index ensures accurate checking of layout at cell, IP, place and route block, and full-chip prior to tapeout
• Trial-OPC interfaces with foundry/IDM process technology data kit for realistic layout verification and process sensitivity analysis
• Performs yield enhancing techniques such as SRAF insertion, line/spacing re-targeting
• Effective gate W/L simulation and extraction, analysis and back-annotation to SPICE for electrical impact
• Built-in design-based yield limiting pattern checks without generating complex edge-based DRC scripts
  • Via analysis for excessive/shortage of via, stack/overlap via, via farm, etc.
  • Metal lines analysis
  • CMP analysis that are difficult to implement in standard DRC rule files
• Plug-and-play to third-party existing DRC verification with easy to setup tech file
  • Tightly integrates into SiCanvas’ Laker layout editor to provide assist in fixing hotspots
• DFM Analyzer reports pertinent information and guidelines for hotspot removal and layout optimization

NanoScope-DFP Flow

Request the NanoScope-DFP™ Product Sheet